Field of the Invention
The present invention relates to an imaging device.
Description of Related Art
A constitution described in Japanese Unexamined Patent Application, First Publication No. 2011-55196 is known as an example of an imaging device using a tdcSS (time to digital converter Single Slope) type AD conversion circuit in which a TDC (Time to Digital Converter) type AD conversion circuit and an SS (Single Slope) type AD conversion circuit are combined. FIG. 16 illustrates a part of a constitution of a tdcSS type AD conversion circuit according to a first conventional example. A constitution and an operation of a circuit illustrated in FIG. 16 will be described below.
The circuit illustrated in FIG. 16 includes a comparator 1031, a latch section 1033, a counter 1034, and a buffer circuit BUF. The comparator 1031 includes a voltage comparator COMP to which a reference signal Ramp decreasing with the lapse of time is input along with an analog signal Signal to be subjected to AD conversion and which outputs a comparison signal CO based on a comparison result of the analog signal Signal with the reference signal Ramp. The latch section 1033 includes a plurality of latch circuits L_0 to L_7 that latch logic states of a plurality of phase signals CK[0] to CK[7] having different phases. The counter 1034 includes a counter circuit CNT that performs a counting operation on the basis of the phase signal CK[7] output from the latch circuit L_7. A control signal RST is a signal for resetting the counter circuit CNT.
In the comparator 1031, a time interval (magnitude in a time axis direction) based on the amplitude of the analog signal Signal is generated. The buffer circuit BUF is an inverting buffer circuit that inverts and outputs an input signal.
The latch circuits L_0 to L_7 of the latch section 1033 are in an enabled (effective, active) state and output the input phase signals CK[0] to CK[7] without any change when a control signal Hold from the buffer circuit BUF is in an H state (high state). The latch circuits L_0 to L_7 are switched to a disabled (ineffective, hold) state and latch the logic states of the input phase signals CK[0] to CK[7] when the control signal Hold from the buffer circuit BUF is changed from the H state to an L state (low state).
The operation of the circuit according to the first conventional example will be described below. FIG. 17 illustrates waveforms of a reference signal Ramp, an analog signal Signal, a start pulse StartP, phase signals CK[0] to CK[7], a comparison signal CO, a control signal Hold from the buffer circuit BUF, and output signals Q0 to Q7 of the latch circuits L_0 to L_7 of the latch section 1033. The horizontal direction in FIG. 17 represents time and the vertical direction in FIG. 17 represents voltage.
First, at a first timing relevant to start of comparison in the comparator 1031, generation of the phase signals CK[0] to CK[7] is started and the generated phase signals CK[0] to CK[7] are input to the latch circuits L_0 to L_7 of the latch section 1033. Since the control signal Hold from the buffer circuit BUF is in the H state, the latch circuits L_0 to L_7 are in the enabled state and output the phase signals CK[0] to CK[7] without any change.
The counter 1034 performs a counting operation on the basis of the phase signal CK[7] output from the latch circuit L_7 of the latch section 1033. In this counting operation, the counted value increases or decreases at a rising or falling timing of the phase signal CK[7]. At a second timing at which the analog signal Signal and the reference signal Ramp are substantially equal to each other in voltage, the comparison signal CO from the comparator 1031 is inverted. After the comparison signal CO is buffered by the buffer circuit BUF, the control signal Hold from the buffer circuit BUF is changed to the L state at a third timing.
Accordingly, the latch circuits L_0 to L_7 are changed to the disabled state. At this time, the logic states of the phase signals CK[0] to CK[7] are latched in the latch circuits L_0 to L_7. The counter 1034 latches the counted value by stopping the operation of the latch circuit L_7. Digital data corresponding to the analog signal Signal is obtained based on the logic states latched by the latch section 1033 and the counted value latched by the counter 1034.
A constitution described in Japanese Unexamined Patent Application, First Publication No. 2012-39386 has also been proposed. FIG. 18 illustrates a part of a constitution of a tdcSS type AD conversion circuit according to a second conventional example. A constitution and an operation of a circuit illustrated in FIG. 18 will be described below.
The circuit illustrated in FIG. 18 includes a comparator 1031, a latch controller 1032, a latch section 1033, and a counter 1034. The comparator 1031 and the counter 1034 are identical to the comparator 1031 and the counter 1034 illustrated in FIG. 16.
The latch controller 1032 includes an inverting delay circuit DLY and an AND circuit AND1 and generates a control signal for controlling the operation of the latch section 1033. A comparison signal CO from the comparator 1031 is input to the inverting delay circuit DLY. The inverting delay circuit DLY outputs a comparison signal xCO_D which is obtained by inverting and delaying the comparison signal CO. The comparison signal xCO_D from the inverting delay circuit DLY and the comparison signal CO from the comparator 1031 are input to the AND circuit AND1. The AND circuit AND1 outputs a control signal Hold_L which is a logical product (AND) of the comparison signal xCO_D and the comparison signal CO.
The latch section 1033 includes latch circuits L_0 to L_7 and an AND circuit AND2. The latch circuits L_0 to L_7 are identical to the latch circuits L_0 to L_7 illustrated in FIG. 16. The AND circuit AND2 outputs a control signal Hold_C which is a logical product (AND) of the comparison signal xCO_D from the inverting delay circuit DLY of the latch controller 1032 and a control signal Enable to the latch circuit L_7.
The operation of the circuit according to the second conventional example will be described below. FIG. 19 illustrates waveforms of a start pulse StartP, phase signals CK[0] to CK[7], a comparison signal xCO_D, a comparison signal CO, a control signal Hold_L from the AND circuit AND1, a control signal Enable, a control signal Hold_C from the AND circuit AND2, and output signals Q0 to Q7 of the latch circuits L_0 to L_7 of the latch section 1033. The horizontal direction in FIG. 19 represents time and the vertical direction in FIG. 19 represents voltage.
An operation different from the operation of the circuit according to the first conventional example will be described below. After a first timing relevant to start of comparison in the comparator 1031 and until the analog signal Signal input to the comparator 1031 and the reference signal Ramp are substantially equal to each other in voltage, the comparison signal CO from the comparator 1031 is in the L state. While the comparison signal CO is in the L state, the comparison signal xCO_D from the inverting delay circuit DLY is in the H state. Since the comparison signal xCO_D from the inverting delay circuit DLY is in the H state and the comparison signal CO from the comparator 1031 is in the L state, the control signal Hold_L from the AND circuit AND1 is in the L state. Accordingly, the latch circuits L_0 to L_6 are in the disabled state.
On the other hand, at the first timing relevant to the start of comparison in the comparator 1031, since the control signal Enable is in the H state and the comparison signal xCO_D from the inverting delay circuit DLY is in the H state, the control signal Hold_C from the AND circuit AND2 is in the H state. Accordingly, the latch circuit L_7 is in the enabled state.
Subsequently, at a second timing at which the analog signal Signal and the reference signal Ramp are substantially equal to each other in voltage, the comparison signal CO from the comparator 1031 is inverted. Since the comparison signal xCO_D from the inverting delay circuit DLY is in the H state and the comparison signal CO from the comparator 1031 is changed from the L state to the H state, the control signal Hold_L from the AND circuit AND1 is changed from the L state to the H state. Accordingly, the latch circuits L_0 to L_6 are in the enabled state.
At a third timing at which a predetermined time elapses from the timing at which the comparison signal CO from the comparator 1031 is inverted, the comparison signal xCO_D from the inverting delay circuit DLY is changed from the H state to the L state. Accordingly, since the control signal Hold_L of the AND circuit AND1 and the control signal Hold_C of the AND circuit AND2 are changed from the H state to the L state, the latch circuits L_0 to L, 7 are in the disabled state.
In the above-mentioned operation, since the latch circuits L_0 to L_6 operate only in the period from the second timing to the third timing, it is possible to reduce current consumption in comparison with the first conventional example.
As a specific constitution of the inverting delay circuit DLY, a constitution employing a so-called delay line in which multiple stages of inverter circuits are connected and which is described, for example, in ITE Technical Report Vol. 37, No. 29 is considered.